IES5501 extends and expands your I²C, 2-Wire, SMBus, PMBus, IPMB

Using analog design principles, the IES5501 is a true bi-directional bus buffer for use in 2- wire bus systems such as I²C, SMBus, PMBus & IPMB etc*. The function of the bus buffer is to extend the bus load limit by buffering the Clock (SCL) and Data (SDA) lines.

The IES5501 simplifies the design process in a 2-wire bus system; we have put the work into the chip to make your job easy.

• Dual bi-directional unity gain buffer
• Fully I²C compliant & supports a wide range of 2-wire standards
• Doesn't impose additional restrictions
  on logic levels
• Very low input to output offset voltages
• Multiple bus buffers allowed in cascade,
  multi-drop or "daisy chain" fashion
• Compatible with all other classes
  of 2-wire bus buffer
• Wide range of allowed bus voltages
  (1.8V to 15V)

• Level shifting between bus voltages
  (1.8V to 15V)
• Superior response times
• Plugs in to live backplanes
• Chip enable allows bus disconnection
• No minimum bus capacitance requirement
• Low current stand-by mode when not enabled
• Application/removal of power to IC will not interfere with other bus activity
• Available in SO-8 and MSOP-8

What does the feature set mean for the 2-wire bus designer? Click here for more.

• Telecommunications Systems
  (inc. ATCATM)
• Radial IPMB architectures
• Power Management System
• Backplane Management / Interconnect
• Desktop and Portable Computers
  (inc. RAID)
• Compact PCIRExpress

• 2-Wire Bus Switch/Multiplexing Applications
• Automotive Accessories (up to 15V)
• Building Automation
• TV / Projector / Monitor interconnection
• Game Consoles / Boxes
• TV / Projector / Monitor interconnection
• Game Consoles / Boxes
• Gaming Machine Networks

• Bus Buffer family
• Applications
• Bus information
• Bus Buffer links
• FAQ
• Ask the Expert

• IES5501 datasheet
• Application Note AN101
• Application Note AN102
• Application Note AN103

• Package & Soldering
• Tape & Reel - MSOP-8
• Tape & Reel - SO-8
• RoHS
• Contact Us

Feature Set

What this means for the 2-wire bus designer

- Dual bi-directional unity gain buffer

The IES5501 bus buffer is a true 2-wire bus component so it becomes a seamless addition to your 2-wire bus design.

- Fully I2C compliant & supports a wide range of 2-wire standards

It doesn't matter what 2-wire bus you are using, the IES5501 is easy to incorporate into your design.

- Doesn't impose additional restrictions on logic levels

If there are additional restrictions on logic levels, the design process gets harder and more involved, the IES5501 doesn't impose any additional restrictions.

- Very low input to output offset voltages

A low input to output offset voltage (hence a large built in noise margin) allows your bus to go further as there is a maximum allowable low logic level specified for 2-wire buses.

- Multiple bus buffers allowed in cascade, multi-drop or "daisy chain" fashion

The result of the low input to offset voltage is that the bus buffers (unlike most of the competition) can plug together in a cascade fashion. This means the bus can expand further with more peripheral ics and with longer bus lines.

- Compatible with all other types of 2-wire bus buffer

Sometimes different bus buffer types are required to build a 2-wire bus depending on the application, the IES5501 can connect to all of these effectively and easily.

- Wide range of allowed bus voltages (1.8V to 15V)

Using analog design techniques, the bus buffer is robust because it handles a wide voltage range. This also enables its use in a wider range of applications.

- Level shifting between bus voltages (1.8V to 15V)

The bus buffer can double as a bus voltage translator, expanding the use of the bus buffer in many areas of your 2-wire bus design.

- Superior response times

The IES5501 reacts fast and thus reduces the restrictions placed on a bus, increasing the ease of integration.

- Plugs in to live backplanes

Using the enable pin, the IES5501 can be plugged into live backplanes.

- Chip enable allows bus disconnection

Individual sections of the bus can be brought on line successively, meaning a controlled start up can be achieved using a diverse range of components, operating speeds and loads.

- Low current stand-by mode when not enabled

The bus buffer consumes a low amount of power when in standby mode; therefore a lower power can ease your design constraints.

- Application/removal of power to IC will not interfere with other bus activity

The unique design of the IES5501 ensures the bus activity will not be affected by the application and removal of power, making your design process easy.

- Available in SO-8 and MSOP-8

Small packages take up less board space and the identical pin outs with various Linear Technology and NXP parts allow the IES5501 to be a drop in replacement.