IES5501 I2C bus buffer typically has only 30mV of input-output offset (guaranteed < 60mV) Bi-directional bus buffers don't receive information to set the data direction flow. To ensure latching doesn't occur (one of an I2C designer's worst enemies) the output voltage on the data lines must be larger than the input voltage. Many buffers including the P82B96 use 'fixed' input and output voltages. If the P82B96 bus buffer input signal is below 0.5V the output is set at 0.6V. The IES5501 is different and creates an ultra-low 'input-output offset' voltage using unique analog design principles. The IES5501 thus ensures the output is typically only 30mV larger than its input. If the input to the IES5501 is equal to or less than 30% of the supply voltage, the output will be equal to the input plus typically only 30mV (60mV is worst case). | And with a power supply of 3.3V, the IES5501 will still be able to accept an input of up to 0.99V. Compliant I2C Switching Levels
All compliant I2C devices are required to have a low level output voltage below 0.4V. When a device isn't compliant with the I2C specification its performance in a system can be affected because of smaller safety margins (also known as 'noise' margin).
Many bus buffers do not meet this specification because of their fixed input-output offsets. The IES5501 is I2C compliant with the low-level requirements of I2C and its output will also be compliant (provided input levels are kept just below the specification). Refer to the ATCA page for more information |
